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Verification of correctness of control programs is an essential task in the development of space electronics; it is difficult and typically outweighs design and programming tasks in terms of development hours
This experience report presents a verification approach designed to help spacecraft engineers reduce the effort required for formal verification of low-level control programs executed on custom hardware. You implement the semantics of a custom industrial instruction-set architecture in Haskell as an EDSL and perform symbolic execution of machine code programs to generate verification conditions which are later discharged with an SMT solver.
Using this methodology, you verify the functional correctness of programs and perform worst-case execution time analysis.
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